1. Field of the Invention
The invention relates to an image processing chip and an image processing system, and particularly relates to an image processing chip and an image processing system having a serial packet transmission interface.
2. Description of Related Art
In the conventional related art, a high speed transmission interface transmitting with serial packets has the advantages of having a high transmission rate and a less transmission pin count. In order to enhance the reliability of data transmission, a differential signal may be further used for transmission so as to mitigate the influence caused by the electromagnetic interference (EMI). Besides, in some image processing systems, an additional image processing chip is often required to enhance the image quality or carry out additional image processing on the original image, such as noise suppression or depth calculation. However, in some scenarios, the image processing chip is not required to carry out image processing but is only required to transmit the received original image to another processing chip.
In order to transmit original image data to another processing chip, it is common to add a bypass between an input end and an output end of an image processing engine in the image processing chip. Accordingly, the original image data may bypass the image processing engine without being modified. However, under such circumstance, a transmission interface controller of the image processing chip is still supplied with power and remains turned on in order to packetize and depacketize the original image data transmitted through the serial packet transmission interface.